1. Field of the Invention
The present invention relates to a non-volatile semiconductor memory device, and particularly to a configuration for reading data at high speed in a non-volatile semiconductor memory device. More particularly, the present invention relates to a configuration for reading data in a non-volatile semiconductor memory device having insulating film charge trapping memory cells each accumulating charges in an insulating film.
2. Description of the Background Art
As a memory storing information in a non-volatile manner, there has been available a collective erasure type EEPROM (electrically erasable and programmable read only memory) having memory cells each constituted of a stacked gate field effect transistor. In the collective erasure type EEPROM or a flash memory, charges are accumulated in a floating gate, made of, for example, polysilicon, insulated from the surroundings and information is stored by altering a threshold voltage of a memory cell transistor according to an accumulated quantity of charges therein.
In the structure of such non-volatile memory cell utilizing a stacked gate field effect transistor, a large electrical stress is applied, in data rewriting, to a tunneling insulating film between a floating gate and a semiconductor substrate region, leading to degradation in the tunneling insulating film. If a defect occurs in such a tunneling insulating film, a charge accumulated in a floating gate is likely to leak out for causing destruction of storage data.
xe2x80x9cAn insulating film charge trapping non-volatile memory cellxe2x80x9d accumulating charges in an insulating film is proposed, as a substitute for a cell structure of a stacked gate field effect transistor that uses a floating gate as a charge accumulating medium.
FIG. 12 is a diagram schematically showing a sectional structure of a conventional insulating film charge trapping memory cell. In FIG. 12, an insulating film charge trapping memory cell includes: buried diffusion layers 901a and 901b formed on a surface of a semiconductor substrate region 900; a multi-layer insulating film 903 formed between buried diffusion layers 901a and 901b; and an electrically conductive layer 904 formed on multi-layer insulating film 903. Diffusion layers 901a and 901b are formed extending in a column direction and used as bit lines. Conductive layer 904 is formed extending in a row direction, and used as a word line to transmit a row select signal and further as a control gate of a memory cell.
Multi-layer insulating film 903, though placed extending in the direction of a word line, is depicted in FIG. 12 as being separated for each memory cell in row direction, in order to emphasize a charge accumulating region of one bit memory cell.
Multi-layer insulating film 903 has a multi-layer structure composed of an oxide film, a nitride film and an oxide film, to accumulate charges in a region of the nitride film. Bit line insulating films 902a and 902b for isolation of adjacent memory cells are formed on diffusion layers 901a and 901b. 
As will be detailed later, adjacent bit lines are isolated by bit line insulating films 902a and 902b without forming an insulating film for channel isolation. Channel isolation is achieved by a PN junction between a formed channel and a substrate region.
In the memory cell structure shown in FIG. 12, a mobility of a charge is small in the insulating film accumulating charges, and therefore, a charge accumulating region is extremely localized. Accordingly, as shown by regions at BT1 and BT2 in FIG. 12, two charge accumulating regions BT1 and BT2 can be formed in one memory cell, thereby enabling storage of 2 bit data in one memory cell.
FIG. 13 is a diagram schematically showing a planar layout of the memory cell shown in FIG. 12. In FIG. 13, there are shown three word lines WL0 to WL2 and three bit lines BL0 to BL2 as representatives. Word lines WL0 to WL2 extend in the row direction and are connected to memory cells arranged on respective rows. Bit lines BL0 to BL2 extend in the column direction and are connected to memory cells arranged on respective columns. Each of bit lines BL0 to BL2 is shared by memory cells adjacent to each other in the row direction.
Multi-layer insulating film 903 is placed in row direction in parallel to and below word line WL (denoting WL0 to WL2 generically). In FIG. 13, charge accumulating regions 905 formed of multi-layer insulating film 903 are shown being arranged between bit lines in a similar manner to the structure shown in FIG. 12, in order to emphasize a charge accumulating region of each memory cell. In FIG. 13, regions 905 hatched by oblique lines are used as charge accumulating regions. Therefore, a nitride film may be formed only in charge accumulating regions 905 hatched by oblique lines. In one charge accumulating region 905, there are formed effective charge accumulating regions (BT1 and BT2) in which charges corresponding to stored data are accumulated. The effective charge accumulating regions are referred to as right and left bit regions in the following description and data stored in these regions are referred to as a right bit and a left bit, respectively.
Bit lines BL0 to BL2 each shared by adjacent memory cells. With respect to one memory cell, one bit line is used as a data line for reading data and the other is used as a source line. A common bit line is used as a data line or a source line, depending on a data access target region.
As shown in FIG. 13, a bit line is just provided corresponding to each memory cell column, without a necessity of a dedicated source line. Dissimilar to a conventional stacked gate transistor cell structure, in which charges are accumulated in the polysilicon floating gate, no source line is required, thereby achieving a reduced occupation area of a memory cell. When a design minimum size is indicated F, for example, a pitch between bit lines is represented by 2xc3x97F and a pitch between word lines is also represented by 2xc3x97F. Accordingly, in FIG. 13, a memory cell region 910 represented by broken lines occupies an area of 2Fxc3x972F.
Since 2 bit data is stored in one memory cell region 910, an effective occupation area of a memory cell is 2xc3x97F2. Furthermore, by changing a quantity of electrons injected into the multi-layer insulating film, a threshold voltage can be changed over multiple levels to enable not only storage of multi-valued data but also more decrease in effective area of a memory cell.
Specifically, in a case where a quantity of injected charges in one effective charge accumulating region (the right bit region or the left bit region) is divided into two levels (a programmed state and an erased state), an effective occupation area of a memory cell is 2xc3x97F2. In a case where a quantity of injected charges in one effective charge accumulating region is divided into four levels, 2 bit data is stored in one effective charge accumulating region. 4 bit data is stored in one memory cell, and an effective occupation area of a memory cell is 1xc3x97F2. In a case where an injected charge quantity in an effective charge accumulating region is set over eight levels, an effective occupation area of a memory cell is 0.5xc3x97F2.
Referring to FIG. 14, description will now be given of a write (programming) and read operations of data. In FIG. 14, binary data is stored in each of right bit region BT1 and left bit region and BT2. Multilayer insulating film 903, as shown in FIG. 14, includes: a lower side oxide film 903a formed on the surface of semiconductor substrate region 900; a nitride film 903b formed on lower side oxide film 903a; and an upper side oxide film 903c formed on nitride film 903b. Charges are accumulated in nitride region 903b. 
Electrically conductive layer (referred to as conductive layer or gate electrode layer hereinafter) 904 functions as a control gate of a memory cell and receives a signal from a word line select circuit not shown.
When electrons are accumulated in right bit region BT1, a voltage of, for example, 9V is applied to control gate (gate electrode layer) 904 and a voltage in the range from 4.5 to 6 V is applied to a diffusion bit line region (impurity region) 901b. Diffusion bit line region (impurity region) 901a is set to ground voltage level. In this state, a channel is formed at the surface of substrate region 900 according to a voltage applied to gate electrode layer 904 and a current I flows from diffusion bit line region 901b toward diffusion bit line region 901a. A current I flowing in the channel region is accelerated by the voltage applied to gate electrode layer 904 in a vertical direction and electrons are injected into and stored in nitride film 903b. Thus, electrons are accumulated in right bit region BT1. In nitride film 903b, an electron mobility is small and therefore right bit region BT1 is formed only in a region in the vicinity of the drain region in self-alignment with the drain region.
On the other hand, when electrons are accumulated in left bit region BT2, diffusion bit line region 901a is supplied with a voltage of in the range from 4.5 to 6 V while diffusion bit line region 901b is set to ground voltage level. Gate electrode layer 904 is supplied with a voltage of 9V. In this case, a current flows from diffusion bit line region 901a to diffusion bit line region 901b and hot electrons generated by a drain high electric field are accelerated by a voltage applied to gate electrode layer 904 and stored in nitride film 903b. Thereby, electrons are accumulated in left bit region BT2.
That is, in program operation, channel hot electrons (CHE) are generated and trapped in nitride film 903b. The state where electrons are injected into the charge accumulating region is referred to as a programmed state (a written state). In programmed state, since electrons are injected in an effective charge accumulating region, a threshold voltage of a memory cell transistor rises in that region.
In data reading, a current I is caused to flow in a memory cell in a direction opposite to that in program operation as shown with an arrow in FIG. 14. That is, when stored data in right bit region BT1 is read out, diffusion bit line region 901a is supplied with a voltage, for example, in the range from 1.5 to 2 V while diffusion bit line region 901b is set to ground voltage level. Gate electrode 904 is supplied with a voltage of, for example, 4 V. In this case, a punch-through is caused due to a widened depletion layer in left bit region BT2 and a threshold voltage in a region in the vicinity of left bit region BT2 exerts no influence on a read current.
In other words, when a current flows from diffusion bit line region 901a to diffusion bit line region 901b in data read operation, a current quantity flowing through the channel region is determined according to a quantity of electrons accumulated in right bit region BT1. Thereby, data stored in right bit region BT1 can be read out.
When data stored in left bit region BT2 is read out, diffusion bit line region 901b is supplied with a voltage in the range from 1.5 to 2 V while diffusion bit line region 901a is set to ground voltage level. Gate electrode layer 904 is supplied with a voltage of the order of 4V. In this case, in a region in the vicinity of right bit region BT1 at the substrate surface region punch-through is caused at the surface of the substrate region and merely the depletion layer is widened. A current flows between diffusion bit lines 901b and 901a according to a quantity of electrons accumulated in left bit region BT2. By detecting a magnitude of the current, data stored in left bit region BT2 can be read out.
Generally, a direction in which a current flows in programming in a memory cell is referred to as a forward direction and a direction in which a current flows in data reading in the memory cell is referred to as a reverse direction. In FIG. 14, as shown by arrows, a relationship between forward and reverse directions for right bit line region BT1 is inverted for left bit line region BT2.
In an operating mode of erasing stored data, various kinds of erase methods have been proposed. One method is that a current is caused to flow in the reverse direction to produce channel hot holes, to inject the channel hot holes into a nitride film, and to recombine accumulated electrons and hot holes with each other to neutralize stored electrons. A second method is that a voltage is applied between nitride film 903b and gate electrode layer 904 to extract electrons accumulated in nitride film 903b through gate electrode layer 904. Since gate electrode layer 904 constitutes a word line and is driven by a row select circuit not shown, electrons are eventually extracted by the row select circuit in the second method. A third method is that a current is caused to flow between nitride film 903b and a drain region (a diffusion bit line) by a (inter-band) tunneling current to extract electrons from nitride film 903b. As for an erase operation, any of erase methods may be employed.
FIG. 15 is a diagram showing an electrically equivalent circuit of a memory cell and applied voltages in program operation. In FIG. 15, memory cells arranged in two rows and three columns representatively. In FIG. 15, a memory cell MC is constituted of a floating gate transistor. In the floating gate transistor, the floating gate is formed not with polysilicon but with nitride film (903b). Word lines WLa and WLb are provided corresponding to the respective memory cell rows and bit lines BLa to BLc are provided corresponding to the respective memory cell columns.
Now, consideration is given to a program operation on right bit region BT1 of memory cell MC1 placed, corresponding to word line WLb, between bit lines BLb and BLc. Data writing (programming) is performed by flowing a current in the forward direction. In this case, bit line BLc is supplied with a voltage in the range from 4.5 to 6 V while bit line BLb is held at ground voltage level. Bit line BLa is maintained in a floating state. Word lines WLa and WLb are set to 0 V and 9 V, respectively. In this state, in memory cell MC1, a current flows from bit line BLc to bit line BLb to produce channel hot electrons, e, and the electrons, e, are stored in right bit region BT1.
In memory cell MC2 adjacent to memory cell MC1 in the row direction, bit line BLa is in the floating state and no channel current flows, and therefore no channel hot electron is produced and no programming is performed.
In memory cell MC3 adjacent to memory cell MC1 in the column direction, word line WLa is maintained at ground voltage level, a memory cell transistor maintains a non-conductive state, no channel current flows and no programming is performed.
In a configuration in which a bit line is shared by memory cells adjacent to each other in the row direction as well, programming can be correctly performed only on a memory cell of programming target.
FIG. 16 is a diagram showing applied voltages in data reading in the memory arrangement of FIG. 15. In FIG. 16, when data stored in right bit region BT1 of memory cell MC1 is read, bit line BLb is supplied with a voltage in the range from 1.5 to 2 V, while bit line BLc is set to ground voltage level. Bit line BLa is maintained in the floating state. Word lines WLa and WLb are set to 0 V and 4 V, respectively. In this state, a current I flows from bit line BLb to bit line BLc according to a quantity of electrons accumulated in right bit region BT1 of memory cell MC1. A magnitude of the current I is detected to read data stored in right bit region BT1.
In this case, bit line BLa is in floating state and no current flows in memory cell MC2 even if a read voltage in the range from 1.5 to 2 V is applied onto bit line BLb. Therefore, a current I of a magnitude according to data stored in right bit region BT1 of memory cell MC1 can be caused to flow with correctness.
When data in left bit region BT2 (left bit) of memory cell MC1 is read out, bit line BLc is supplied with a voltage in the range from 1.5 to 2 V, while bit line BLb is supplied with ground voltage.
FIG. 17 is a diagram schematically showing a configuration of data reading section in a conventional non-volatile semiconductor memory device. In FIG. 17, the data reading section includes; a constant current source 920 coupled with a bit line BL corresponding to a selected column through column select gate 915 to supply a read voltage to selected bit line BL together with a constant current IR in data reading; a capacitive element 921 charged by a shunt current Is from constant current source 920; and an amplification circuit 922 producing internal read data RD according to a charged voltage of capacitive element 921. Amplification circuit 922 is constituted of, for example, a differential amplification circuit and compares a charged voltage of capacitive element 921 with a prescribed reference voltage to produce binary read data RD.
Bit line BL is connected to a virtual source line VSL through memory cell MC. Virtual source line VSL is constituted of a bit line BL of an adjacent column and virtual source line VSL, in data reading, is maintained at ground voltage level.
In the configuration of the internal data reading section shown in FIG. 17, a current Ib flowing from bit line BL to virtual source line VSL changes in magnitude according to stored data of memory cell MC. In response, a magnitude of current Is flowing to capacitive element 921 changes. Therefore, a voltage of capacitive element 921 charged in a prescribed period changes according to a stored data of memory cell MC. By detecting a charged voltage of capacitive element 921 in amplification circuit 922 to amplify, internal data RD is produced. In FIG. 17, capacitive element 921 is discharged to ground voltage level through a discharging switch not shown once prior to data reading.
FIG. 18 is a graph roughly showing a correspondence relationship between a charged voltage of capacitive element 921 shown in FIG. 17 and a read data from a memory cell. In FIG. 18, the ordinate indicates a voltage V, while the abscissa indicates a time t.
When a selected memory cell MC is in the erased state, a threshold voltage thereof is low and a comparatively large current Ibe flows. Therefore, a major part of constant current IR from constant current source 920 flows through memory cell MC, and a charging current Ise to capacitive element 921 is small. When memory cell MC is in erased state, charged voltage Vse of capacitive element 921 rises slowly.
When selected memory cell MC is in the programmed state, a threshold voltage thereof is high and only a small current Ibp flows as bit line current Ib. In this case, comparatively large current Isp flows from constant current source 920 to capacitive element 921 to raise greatly charged voltage Vsp of capacitive element 921.
Usually, in a memory cell in erased state, a current of about 40 xcexcA flows, while in a memory cell in programmed state, a current of about 5 xcexcA flows.
In order to discriminate between two states of erased sate and programmed state, amplification circuit 922 is activated when a potential difference between the two states increases sufficiently. In FIG. 18, there is shown a case where amplification circuit 922 is activated at time point t0. At time point t0, a large potential difference occurs between when data in the erase state is read out and when data in programmed state is read out, and therefore, stored data in a memory cell can be read stably.
A current flowing through memory cell MC, however, is on the order of xcexcA. Therefore, a time period till t0, or the charging time for the capacitive element 921 has to be set sufficiently long, in order to read out data correctly in consideration of a sufficient margin. Hence, there is a problem that read data cannot be produced at high speed and a high speed access can not be achieved.
Especially, in a case where a read sequence is used in which one bit memory cell is selected and 2-bit data stored in the one bit memory cell is consecutively read out internally to output the data in parallel external, a problem arises that such a multi-valued data cannot be read out at high speed.
In a configuration where in data reading, capacitive element 921 is precharged to a prescribed voltage and a current is supplied into a selected bit line according to a charged voltage of capacitive element 921 as well, a necessity arises for delayed activation of amplification circuit 922, in order to discriminate sufficiently in the charged voltage level of a capacitive element between the programmed state and the erased state of a memory cell, resulting in a similar problem,
It is an object of the present invention to provide a non-volatile semiconductor memory device capable of reading data at high speed.
It is another object of the present invention to provide a non-volatile multi-valued memory capable of reading internal data at high speed.
It is a specific object of the present invention to provide a non-volatile semiconductor memory device of an insulating film charge trapping memory cell structure capable of reading internal data at high speed.
A non-volatile semiconductor memory device according to a first aspect of the present invention includes: a plurality of non-volatile memory cells, arranged in rows and columns, each for storing data in a non-volatile manner. Each non-volatile memory is configured of an insulated gate transistor having a threshold voltage set according to stored data. The threshold voltage attains at least a first state corresponding to a data at a first logical level and a second state corresponding to data at a second logical level.
The non-volatile semiconductor memory device according to the first aspect of the present invention further includes: a plurality of bit lines provided corresponding to respective memory cell columns, and connected to memory cells on the respective corresponding columns; a read current generating circuit, in data reading, for supplying a current into a bit line of a selected column; and a reference current generating circuit for generating a reference current. The reference current has a magnitude of the average of a first read current flowing through the bit line of a selected column when a memory cell in the first state is selected and a second read current flowing through the bit line of a selected column when a memory cell in the second state is selected, with respect to the read current corresponding to a current flowing into the bit line of the selected column from the read current generating circuit.
The non-volatile semiconductor memory device according to the first aspect of the present invention further includes: a comparison circuit for comparing the reference current from the reference current generating circuit with a read current from the read current generating circuit to generate a signal corresponding to a result of the comparison; and an internal read circuit for generating internal read data according to an output signal of the comparison circuit.
A non-volatile semiconductor memory device according to a second aspect of the present invention includes: a plurality of non-volatile memory cells, arranged in rows and columns, each for storing data in a non-volatile manner. Each non-volatile memory cell has an insulated gate transistor having a threshold voltage set according to stored data. A threshold voltage of each memory cell attains at least a first threshold voltage corresponding to stored data at a first logical level and a second threshold voltage corresponding to stored data at a second logical level.
The non-volatile semiconductor memory device according to the second aspect of the present invention further includes: a plurality of bit lines provided corresponding to respective memory cell columns, and connected to memory cells on the corresponding columns; and a reference current generating circuit for generating a reference current. The reference current has a magnitude of the average, in data reading, of a first current flowing through a memory cell having the first threshold voltage when the memory cell having the first threshold voltage is selected and a second current flowing through a memory cell having the second threshold voltage when the memory cell having the second threshold voltage is selected.
The non-volatile semiconductor memory device according to the second aspect of the present invention further includes: a constant current generating circuit for generating a constant current having a prescribed magnitude; a comparison circuit for supplying the constant current into a bit line of a selected column as read current to generate a signal corresponding to a difference between the read current and the reference current; and an internal read circuit for generating internal read data according to an output signal of the comparison circuit.
A non-volatile semiconductor memory device according to a-third aspect of the present invention includes: a plurality of non-volatile memory cells, arranged in rows and columns, each including a memory transistor having a threshold voltage changed according to stored data; a plurality of bit lines provided corresponding to the memory cell columns, and connected to memory cells on the corresponding columns; a read current supply current circuit for supplying a current into a bit line of a selected column; a reference current generating circuit for generating a reference current; and a comparison circuit for comparing a current flowing through a memory cell on the selected column with the reference current, to generate a signal indicating a result of the comparison.
A non-volatile semiconductor memory device according to a fourth aspect of the present invention includes: a plurality of non-volatile memory cells, arranged in rows and columns, each including a transistor having a threshold voltage set according to stored information, and each storing information in a non-volatile manner; a plurality of bit lines, provided corresponding to the memory cell columns and connected to memory cells on the corresponding columns, each being shared by memory cells on adjacent columns; a current supply circuit coupled to a first bit line of a selected column to supply a current into the first bit line; and a sense amplifier coupled to a second bit line of the selected column to generate internal read data according to a current flowing through the second bit line.
A non-volatile semiconductor memory device according to a fifth aspect of the present invention includes: a plurality of non-volatile memory cells, arranged in rows and columns, each including a transistor having a threshold voltage set according to stored information and storing information in a non-volatile manner; a plurality of bit lines, provided corresponding to the memory cell columns and being shared by memory cells on adjacent columns, connected to memory cells on the corresponding columns; a current supply circuit coupled to a first bit line of a selected column to supply a current into the first bit line; a reference power supply coupled to a second bit line of the selected column; and a sense amplifier coupled to the first bit line in parallel to the current supply circuit to generate internal read data according to an applied current.
By performing reading of internal data with a current sensing scheme in data reading, there is no need to consider a margin for a charging time for a capacitive element, thereby enabling execution of reading of internal data at high speed.
By generating a current having an intermediate value between two values of stored data in a memory cell as a reference current to compare the reference current with a read current flowing in the memory cell in selection of a memory cell, stored data in the memory cell can be correctly determined. The same margin can be secured for data corresponding to erase state and for data corresponding to programmed state, thereby enabling determination of a logical level of read data stably at high speed.
By detecting a current flowing from the first bit line to the second bit line through a memory cell, a current corresponding to a state of a selected memory cell can be correctly detected, thereby enabling reading memory cell data internally at high speed.
By coupling the sense amplifier to a bit line of a selected column in parallel to the current supply circuit to detect a current from the current supply circuit in the sense amplifier, a current corresponding to a current flowing in a selected memory cell can be supplied to the sense amplifier, thereby enabling reading stored data in a memory cell correctly at high speed.
The foregoing and other objects, features, aspects, and advantages of the present invention will become apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.